Improved shift register having (n/2 - 1) stages for digitally synthesizing an n-phase sinusoidal waveform

ABSTRACT

A method is disclosed for calculating appropriate output resistor values in the summing circuitry of a transversal filter featuring a shift register configured to digitally synthesize sinusoidal waveforms. Output resistor values calculated according to the method result in an improved circuit by allowing the elimination of the otherwise required last stage of the shift register and a reduction with respect to the prior art in the ratios of the values of the output resistors.

United States Patent 1191 Condon 5] Apr. 2, 1974 [54] IMPROVED SHIFTREGISTER HAVING (N/Z 3,482,190 12/1969 Brenin 333/29 1 STAGES FORDIGITALLY 3,221,170 7/1970 Leuthold et a1. 328/37 SYNTHESIZING ANN-PHASE SINUSOIDAL 22: 3; WAVEFORM l ORlilGN PATENTS [75] Inventor:Joseph Henry Condon, Summit, NJ.

1,194,899 6/1965 Germany 328/14 [73] Assignee: Bell TelephoneLaboratories,

Incorporated, Murray Hill, NJ. OTHEZR PTUBUCATIONS Peckels et al.:Subst1tut1on of a delay line for a whole F1199: 1972 bank of filters,IBM Technical Discl. Bull. Apr. 1966, 21 Appl. No.: 301,430 Pages1498-1499- Primary ExaminerFelix D. Gruber [52] U.S. Cl 235/197,235/l50.53, 328/27, Attorney, Agent, phelan 328/37 {51] [1 11. CI G06g7/28 57 ABSTRACT [58] Field of 'gg A method is disclosed for calculatingappropriate out- T 1 put resistor values in the summing circuitry of atransversal filter featuring a shift register configured to dig- [56]References Cited itally synthesize sinusoidal waveforms. Output resistorUNITED STATES PATENTS values calculated according to the method resultin an 3,579,117 5/1971 Norris 328/37 improved circuit by allowing theelimination of the 3,623,160 1 H1971 Giles 340/347 DA otherwise requiredlast stage of the shift register and a y reduction with respect to theprior art in the ratios of erreau 3,543,009 11/1970 Voelcker, Jr. 333/29the values of the output reslstors 3,292,110 12/1966 Becker et a1 333/296 Claims, 6 Drawing Figures 20' s' s' s 1 l 2 3 d (t) o 1 271 11 1 a 1|l 1 1 7 F I 1 d 1 I0 I J1 1r 1 I I 50 d e d m; (k)} ,5 I 1 2 3 1 1.ATENTEDAPR 2mm 4 I 3801.807

SHhEIJ-UFZ N I 20 s s s ("U 5 RIP I L50 T T I l I 2 3 I l Ii A FIG. %RR1? (2 a g? (PRIOR ART) FIG. 2 (PRIOR ART) FIG. 3 (PRIOR ART)PATENTEDAPR 2 I974 SHEEI 2 OF 2 FIG. 6

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IMPROVED SHIFT REGISTER HAVING (N/2 l) STAGES FOR DIGITALLY SYNTHESIZINGAN N-PI-IASE SINUSOIDAL WAVEFORM BACKGROUND OF THE INVENTION 1. Field ofthe Invention This invention relates, generally, to the art ofdigitalto-analog waveform conversion circuits and, more specifically, toa method for calculating output resistor values in the summing circuitryof an improved transversal filter which is configured to digitallysynthesize sinusoidal waveforms.

2. Prior Art Over the past few years it has become increasingly apparentto circuit designers that, in applications where snall amounts ofharmonic distortion can be readily tolerated, sinusoidal waveforms aremost economically and dependably generated with digital circuitry. Onesuch application lies in telephone station sets which provide multitonedialing service. In the past, the multifrequency dialing signalsutilized in such station sets have been generated with analog circuitry.More recently, however, this analog circuitry has been replaced inexperimental station sets with digital circuitry which synthesizes thedialing waveforms by adding together differently shifted and weightedcomponents of digital waveforms having the same frequencies as thedialing waveforms.

This digital circuitry has been advantageously constructed in thegeneral form of a transversal filter which is principally comprised ofan N/2 stage serial shift register. The output of each stage of theshift register is equipped with an output resistor connecting to acommon summing terminal. A digital waveform of the desired frequency fl,is fed into the signal input of the input stage of the shift register.The digital waveform is then shifted along the register at the frequencyNf The digital waveform appearing at the signal output of each stage ofthe shift register is continuously summed with the other such waveformsat the summing terminal in a proportion depending upon the value of theoutput resistor connecting that stage to the summing terminal. As aresult, a digital approximation of the desired dialing waveform appearsat the summing terminal. N is an even integer of a magnitude which isnominally inversely proportional to the level of harmonic content in theresulting dialing waveform. As N is increased toward infinity theharmonic content of the dialing waveform approaches zero; or, expressedanother way, the noise power of the dialing waveform decreases and thepower of the fundamental component of the dialing waveform increases asthe number of stages, N/2, is increased.

A good measure of the quality or lack of harmonic distortion in thesynthesized waveform is the number of differently shifted components, oralternatively, shift register stages, N/2, which contribute tocollectively generate the synthesized waveform.

Additional shift register stages are required to achieve a lowerharmonic content in the synthesized waveform; a reduction in the numberof stages increases the harmonic content of the synthesized waveform.

In prior art circuits of this type, the values of the resistorsconnecting the outputs of the individual shift register stages to thecommon summing terminal have been arrived at by empirical designtechniques. Unfortunately, however, these empirical design techniqueshave proved to be unsatisfactory for a number of reasons. One suchreason is that they have resulted in large ratios between the values ofthe respective output resistors. In certain methods for depositing thinfilm resistors it is desirable that the ratios between the values of theresistors be as close to unity as is possible. Since it is essentialthat these shift register circuits be suff1- ciently small to beincorporated into telephone station sets, it is desirable that theoutput resistors be of values which facilitate their fabrication as thinfilm structures. It would, therefore, be advantageous to discover amethod for arriving at output resistor values which results in lowratios between the respective output resistor values.

Commercial implementation of these circuits in multitone station setswould result in the eventual manufacture of literally millions of theseshift register circuits. It would, therefore, enable the manufacturersof the station sets to achieve substantial savings by discovering designtechniques which would eliminate unnecessary hardware requirements inthe shift register circuits. As was pointed out above, however, anyreduction in the number of shift register stages or output resistorsusually results in a deterioration in the quality of the synthesizedwaveform.

It is, therefore, an object of this invention to provide a simple,systematic, analytical, technique for designing the aforedescribed shiftregister circuit with the intent to reduce the hardware requirements ofthe circuit.

It is a further object of the invention to provide a design teehniquefor reducing the hardware requirements of the circuit which will notalso result in an increase in the harmonic content of the synthesizedwaveform.

It is yet another object of the invention to provide a design techniquewhich will facilitate the fabrication of the output resistors in a thinfilm structure by reducing the ratios of the values of the outputresistors.

SUMMARY OF THE INVENTION One aspect of the present invention lies inappropriate values for the output resistors in the summing circuitry ofan (N12) stage shift register circuit which is configured to digitallysynthesize a sinusoidal waveform. More specifically, it has beendiscovered that the values of the output resistors are advantageously R,K/(cos(2 1ri/N+ qr/N) cos(2 1r(i-l)/N 1r/N)) where Nis an even integergreater than or equal to six; 1' is an integral index variablecorresponding to the shift register stage number to which the particularoutput resistor having that subscript number is connected, i runningfrom I to (N12) (beginning at the input stage of the shift register);and K is a constant of proportionality.

Output resistor values in accordance with the first aspect of theinvention allows the elimination of the last stage of the shift registerand its output resistor, resulting in the second aspect of the inventionan improved [(N/ 2 )1 ]-stage circuit which is capable of synthesizingthe desired sinusoid with substantially the same amount of harmonicdistortion as is produced by the prior art, (N/2) stage circuit. Animportant feature of the invention is that a reduction is achieved withrespect to the prior art in the ratios of the largest and smallestoutput resistors required to synthesize any given sinusoidal waveform.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 depicts a schematic diagram ofa generalized, prior art, (N/2) stage shift register circuit configuredfor synthesizing a sinusoidal waveform.

FIG. 2 illustrates a prior art (N/2)-stage shift register circuit, whereN=8.

FIG. 3 shows a sinusoidal current waveform s (t) synthesized by thefour-stage circuit shown in FIG. 2.

FIG. 4 illustrates an [(N/2 l)-stage ]shift register circuit inaccordance with the invention, where N=8.

FIG. 5 depicts the internal voltage waveforms d (t), d (t), and d (t) ofthe circuit shown in FIG. 4 as it responds to a digital input waveformd(t) to synthesize the current waveform s (t).

FIG. 6 shows an [(N/2 2)]-stage shift register circuit which is achievedin accordance with the invention by eliminating the input stage of thecircuit depicted in FIG. 4.

DETAILED DESCRIPTION OF THE INVENTION The prior art (N/2)-stage circuit,shown in generalized schematic form in FIG. 1, is illustrative of thetransversal filter circuits which in the past have been utilized todigitally snythesize sinusoidal waveforms. A sinusoidal waveformsynthesized by the (N/2)-stage circuit shown in FIG. 1 is conveientlycharacterized by N distinct phases" of constant amplitude and equalduration per cycle of the resulting synthesized waveform.

A synthesized sinusoid is generated in the circuit shown in FIG. 1 inthe following manner. A digital signal d(t), such as a square wave,having the same pulse repetition frequency f as the desired sinusoid iscoupled into signal input 10 of input stage 1 of shift register 50. Adigital shifting or clocking signal d(t) having a frequency Nf iscoupled through lead to shifting inputs S through S of stages 1 through(N/2), respectively, of shift register 50. The differently shiftedcomponents of d(t), which appear at the respective output terminals ortaps of shift register stages 1 through (N/2), are coupled to a commonsumming terminal through corresponding ones of output resistors Rthrough R Each such component is summed with the other components atsumming terminal 30 in proportion to the conductance of the particularresistor through which the component is coupled to the summing terminal.The summation of the components results in a synthesized sinusoid S(t)being formed at terminal 30.

The four-stage circuit shown in FIG. 2 is a specific example of thegeneralized circuit shown in FIG. 1. A synthesized current waveform,generated by the fourstage circuit (N=8) shown in FIG. 2, is depicted inFIG. 3. The dashed current waveform shown in FIG. 3 represents thedesired waveform and the stepped waveform s (t) represents thesynthesized approximation of the desired waveform. V represents themagnitude of voltage waveforms appearing at the signal outputs of shiftregister stages 1 thorugh 4, respectively, shown in FIG. 2. As isapparent from FIG. 3, each cycle of the synthesized current waveforms,(t) is characterized by eight distinct phases P -P which are all ofequal duration, (T/8).

Formulation of the current waveform s (t), shown in FIG. 3, by thecircuit shown in FIG. 2, requires the following output resistor values:R 1+ V2) R,,; R R R R and R =(l l 1/ 2 I R is a constant factor found inR through R.,. Although it is not specifically taught in the prior art,it has been observed that the output resistor values in prior art shiftregister circuits of the type shown in FIGS. 1 and 2 satisfy the formulaR, K/(cos 2 vri/N) cos(2 -n'(i1)/N)), (1)

where N is an even integer; i is an index variable corresponding to thenumber of the stage to which the particular output resistor having thatsubscript number is connected, 1' running from 1 to N/2 (beginning atthe input stage of the register); and K is a constant ofproportionality. In the past, deviation from these values would cause anincrease in the harmonic content and a resulting deterioration in thequality of the synthesized waveform. It has been recently discovered,however, that the resistance values of output resistors R, through R aremore advantageously chosen according to the formula (2) where N is aneven integer greater than or equal to six; i is an index variablecorresponding to the number of the stage to which the particular outputresistor having that subscript number is connected,.i== l, 2, (N12)(beginning at input stage 1 of the shaft register), and K is a constantof proportionality.

A variety of advantages are realized by choosing output resistor valuesin accordance with formula (2) rather than formula (1 One such advantageis that the last or (N/2)th stage of the shift register and its outputresistor can be eliminated without introducing additional harmonicdistortion into the synthesized waveform. The reason why the (N2)thstage can be eliminated is that choosing output resistor valuesaccording to formula (2) always results in the value of the outputresistor associated with the (N2 )th stage becoming infinite. The(N/2)th stage is therefore not necessary and the desired sinusoidalwaveform can be synthesized from the remaining [(N/2 l stages of theshift register. Moreover, a synthesized waveform generated by such an[(N/2-l )l-stage circuit is of substantially the same quality orharmonic content as one generated by a corresponding (N/2)-stagecircuit, despite the fact that differently formed approximations of thedesired sinusoidal waveform are generated by the (N/2)-stage and [(N/2-l)]-stage circuits, as is apparent from a comparison of current waveformss,(t) and s (t) depicted in FIGS. 3 and 5, respectively. This importantfeature is achievable in the [(N/2-1 )]-stage circuit for any eveninteger value of N greater than or equal to six.

A more important advantage achieved by selecting the values of theremaining [(N/2-l output resistors according to formula (2) is that theratio of the values of the largest and smallest remaining outputresistors is reduced or minimized with respect to the prior art. Thisfeature is of significant importance in manufacturing this type of shiftregister because, as is pointed out above, manufacturing toleranceconstraints on the output resistors are more easily met as the ratios ofthe respective resistor values decrease.

A comparison of formulas (1) and (2) reveals that formula (2) differsfrom formula l in the respect that the argument of each cosine term informula (2) includes the phase angle (rr/N) radians. The primaryphysical effect of including this phase angle in formula (2), other thanchanging the resulting values of the output resistors, is that awaveform generated by a circuit designed in accordance with formula (2)is shifted in phase by (7T/N) radians with respect to a waveformgenerated by a circuit designed in accordance with formula l A minorphysical effect is that, for the same digital input waveform, theamplitude of the resulting synthesized waveform is decreased slightly byan amount depending upon the value of N. Since the relative phase andamplitude of such waveforms are usually not of any particularsignificance, however, in the type of applications in which suchwaveforms are normally utilized, the reduced hardware requirements areachieved in the [(N/2-l )]-stage shift register at the expense ofadjusting parameters which are under no critical design constraints.

A sinusoidal waveform s (t) (N=8), synthesized in accordance with theinvention in the circuit shown in FIG. 4, is depicted in FIG. 5. Theeight distinct phases per cycle of the waveform are indicated byreference characters P,P As is apparent from FIG. 5, current waveform s(t) is synthesized from three differently shifted and weighted digitalvoltage waveforms d (t), d (t), and d (t), all having a frequency f [f=(lT and a magnitude V. Voltage waveforms d (t), d (t), and d t) arerespectively generated at the outputs of shift register stages 1, 2',and 3 of three-stages serial shift register 50. Waveforms d (t), d (t),and d (t) are generated in response to (a) the coupling of the digitalsignal d(t), having the frequency f through lead 1 into the signal inputof stage 1, and (b) the coupling of the digital shifting signal d(t),having a frequency Nf through lead 20 into shifting inputs S S and S ofstages 1', 2, and 3, respectively. The resulting waveforms d,(t), d (t),and d (t) are coupled through output resistors R,, R and R respectively,to summing terminal 30 to form s-,,(t). The values of resistors R R andR calculated in accordance with formula (2), are as follows: R \QR R Rand R VTR R is a common factor found in R, through R as well as in Rthrough R, (shown in FIG. 2).

A Fourier analysis of current waveform s (t) reveals that it has thesame amount of harmonic distortion as current waveform s,(t), shown inFIG. 3, which is generated by the four-stage prior art shift registercircuit illustrated in FIG. 2. It is therefore apparent that asynthesized sinusoidal waveform having a quality equal to that of s (t),which is generated in a four-stage [(N/2=4)] shift register circuit, canbe generated in but a three-stage [(N/2-l=3)] shift register circuit.Moreover, it is further apparent that the ratio between the largest andsmallest output resistors,

required to generate s (t) in the [(N/Z-I )]-stage shift registercircuit shown in FIG. 4 is reduced with respect to the ratio between thelargest and smallest output resistors,

required to generate s,(t) in the (N/2)stage shift register circuitshown in FIG. 2. As was pointed out in the foregoing review of the priorart, this results in significant advantages in manufacturing the [(N/2-1 )]-stage shift register circuit.

An equivalent embodiment of the invention is achieved which obviates theneed for stage 1 of shift register 50', shown in FIG. 4, without causingany deterioration'in the resultant waveform s (t). In this embodiment ofthe invention, component d (t) is generated externally and fed directlyinto the signal input of stage 2. The circuit shown in FIG. 4 is thenreduced to [(N/22).]-stage register 50", shown in FIG. 6. As can be seenin FIG. 6, shift register 50" features but two shift register stages, 2"and 3", and three resistors R,", R and R whose values are calculated inaccordance with formula (2). Output resistor R is connected directly tothe signal input of shift register stage 2", into which is coupledd,(t). It is apparent, however, that in the equivalent embodiment of theinvention shown in FIG. 6, the summing circuit receives the same numberof differently shifted components as in the embodiment of the inventionshown in FIG. 4. Moreover, it should be further apparent that theamplitudes of the components coupled to the summing circuit in theembodiment of the invention shown in FIG. 6 are the same as in theembodiment of the invention shown in FIG. 4.

integer greater than or equal to six, said circuit comprising:

a shift register having plural serially connected stages;

means for coupling a shifting signal having a frequency Nfi, to each ofsaid stages;

means for coupling a digital signal having a repetition frequency f intothe signal input of a first one of said stages;

a summing terminal; and

no more than [(N/2l)] output resistors, each of said resistorsconnecting from said summing terminal to the signal output of adifferent one of said stages.

2. A shift register circuit comprising:

a plurality of shift register stages connected in a serial string;

means for coupling a shifting signal to the shifting signal input ofeach of said stages;

means for coupling a digital waveform into the signal input of the firststage in said serial string of stages;

a summing terminal; and

no more than [(N/21)] resistors, each of which connects tw said sqt maetst nina an he signal output of a different one of said stages and thevalues of which relate to one another in accordance with the formulawhere N is an even integer greater than or equal to six, i is anintegral index variable corresponding to the number of the stage towhich ,the resistor having that subscript number is connected, i rangingfrom 1 to [(N/2-1 (beginning at the first stage of said string ofstages), and K is a constant of proportionality.

3. A tapped delay circuit for digitally synthesizing a sinusoidalwaveform, comprising:

a serial shift register for providing at tapped signal outputs thereofplural differently delayed components of a digital waveform;

a common summing terminal;

resistive means for coupling said differently delayed components fromsaid tapped outputs to said common summing terminal, including pluralresistors having values in accordance with the formula where i is anintegral index variable, K is a constant of proportionality, and N is aneven integer of greater than or equal to six and of a magnitude selectedin accordance with the degree of harmonic distortion in the resultingsynthesized waveform.

4. A circuit in accordance with claim 3 wherein said shift registercomprises [(N/2-l stages; and

said resistive means includes [(N/2-l output resistors.

5. A circuit in accordance with claim 3 wherein said shift registercomprises no more than [(N/ 2-2 stages; and

said resistive means includes [(N/2-1 output resistors.

6. A circuit in accordance with claim 4 wherein said shift registercomprises [(N/22)] stages; and said resistive means includes no morethan [(N/22)] output resistors.

no more than

1. A circuit for digitally synthesizing a stepped approximation of asinusoidal waveform having a fundamental frequency F0 and having Nphases of equal duration per cycle of the waveform, where N is an eveninteger greater than or equal to six, said circuit comprising: a shiftregister having plural serially connected stages; means for coupling ashifting signal having a frequency Nf0 to each of said stages; means forcoupling a digital signal having a repetition frequency f0 into thesignal input of a first one of said stages; a summing terminal; and nomore than ((N/2-1)) output resistors, each of said resistors connectingfrom said summing terminal to the signal output of a different one ofsaid stages.
 2. A shift register circuit comprising: a plurality ofshift register stages connected in a serial string; means for coupling ashifting signal to the shifting signal input of each of said stages;means for coupling a digital waveform into the signal input of the firststage in said serial string of stages; a summing terminal; and no morethat ((N/2-1)) resistors, each of which commects between said summingterminal and the signal output of a different one of said stages and thevalues of which relate to one another in accordance with the formula RiK/(cos(2 pi i/N + pi /N) - cos(2 pi (i-1)/N+ pi /N)), where N is an eveninteger greater than or equal to six, i is an integral index variablecorresponding to the number of the stage to which the resistor havingthat subscript number is connected, i ranging from 1 to ((N/2-1))(beginning at the first stage of said string of stages), and K is aconstant of proportionality.
 3. A tapped delay circuit for digitallysynthesizing a sinusoidal waveform, comprising: a serial shift registerfor providing at tapped signal outputs thereof plural differentlydelayed components of a digital waveform; a common summing terminal;resistive means for coupling said differently delayed components fromsaid tapped outputs to said common summing terminal, including pluralresistors having values in accordance with the formula Ri K/(cos(2 pii/N + pi /N) - cos(2 pi (i-1)/N + pi /N)), where i is an integral indexvariable, K is a constant of proportionality, and N is an even integerof greater than or equal to six and of a magnitude selected inaccordance with the degree of harmonic distortion in the resultingsynthesized waveform.
 4. A circuit in accordance with claim 3 whereinsaid shift register comprises ((N/2-1)) stages; and said resistive meansincludes ((N/2-1)) output resistors.
 5. A circuit in accordance withclaim 3 wherein said shift register comprises no more than ((N/2-2))stages; and said resistive means includes no more than ((N/2-1)) outputresistors.
 6. A circuit in accordance with claim 4 wherein said shiftregister comprises ((N/2-2)) stages; and said resistive means includesno more than ((N/2-2)) output resistors.